Techn. Inf. - Embedded Hardware/Software Systems

Dipl.-Phys. Domenik Helms

Address:
Domenik Helms
OFFIS
Escherweg 2
26121 Oldenburg
Germany

Telephone:+49-441-9722-284
FAX:+49-441-9722-282
E-Mail:domenik.helms@offis.de

Room: E86
Consultation hour: Freitag 10.00 - 11.00 Uhr

Domenik Helms

 

2008

articles

1.
RT Level Makro Modelling of Leakage and Delay under Realistic PTV Variation
author:
Domenik Helms, Marko Hoyer, Sven Rosinger, Wolfgang Nebel


inproceedings

1.
A Comparison of Approaches for High-level Power Estimation of LUT-based DSP Components
author:
Ruzica Jevtic, Carlos Carreras, Domenik Helms


2.
On Leakage Currents: Sources and Reduction for Transistors, Gates, Memories and Digital Systems
author:
Wolfgang Nebel, Domenik Helms
file:
Nebel_ISLPED08_Tutorial.pdf  


3.
RT Level Makro Modelling of Leakage and Delay under Realistic PTV Variation
author:
Domenik Helms, Marko Hoyer, Sven Rosinger, Wolfgang Nebel


misc

1.
Leakage Models for High Level Power Estimation
author:
Domenik Helms


2.
Verfahren zur Simulation elektrischer Schaltkreise
author:
Domenik Helms, Marko Hoyer


proceedings

1.
RT Level Makro Modelling of Leakage and Delay under Realistic PTV Variation
author:
Domenik Helms, Marko Hoyer, Sven Rosinger, Wolfgang Nebel


2007

inproceedings

1.
Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems
author:
Domenik Helms, Wolfgang Nebel


2.
Modelling the impact of high level leakage optimization techniques on the delay of RT-components
author:
Marko Hoyer, Domenik Helms, Wolfgang Nebel


3.
RTL Power Modeling and Estimation of Sleep Transistor based Power Gating
author:
Sven Rosinger, Domenik Helms, Wolfgang Nebel


4.
System level optimization of static power consumption in nano CMOS circuits
author:
Domenik Helms


5.
System Level Optimization of Static Power Consumption in Nano-CMOS
author:
Domenik Helms


6.
Voltage- and ABB_Island Optimization in High Level Synthesis
author:
Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel


2006

inproceedings

1.
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage
author:
Domenik Helms, Marko Hoyer, Wolfgang Nebel


2.
Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation
author:
Domenik Helms, G?nter Ehmen, Wolfgang Nebel


3.
Leakage Currents in Nanometer CMOS
author:
Wolfgang Nebel, Domenik Helms, Ali Keshavarzi


misc

1.
Intelligentes Powermanagement
author:
Wolfgang Nebel, Domenik Helms


2005

incollections

1.
High-Level Power Estimation and Analysis
author:
Wolfgang Nebel, Domenik Helms


inproceedings

1.
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction
author:
Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel


misc

1.
Leakage Power Modeling, Estimation and Optimization
author:
Domenik Helms


2.
Leakage Power Modeling, Estimation and Optimization
author:
Domenik Helms


2004

inproceedings

1.
Leakage in CMOS Circuits - An Introduction
author:
Helms Domenik, Eike Schmidt, Wolfgang Nebel


2003

inproceedings

1.
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
author:
Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel


2.
Interconnect Driven Low Power High-Level Synthesis
author:
Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel


2002

inproceedings

1.
An Improved Power Macro-Model for Arithmetic Datapath Components
author:
Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel


2.
Low Power Design for SoCs
author:
Wolfgang Nebel, Domenik Helms, Eike Schmidt, Milan Schulte, Ansgar Stammermann